This relates to interface traps within metal oxide semiconductor field effect transistors (MOSFETs); and, in particular, to methods for measuring interface traps in thin gate oxide MOSFETs.
As is known in the art, semiconductor wafers often contain material interfaces, such as between silicon and silicon dioxide (i.e., a Si—SiO2 interface). Contaminants and other defects at the oxide/silicon interface can cause problems in the manufacture and performance of integrated circuits that are fabricated over that interface. These defects, often referred to as interface traps, are capable of trapping and de-trapping charge carriers. Interface traps can have an adverse effect on device performance. For example, an interface trap can cause discrete switching in the source conductance, band-to-band tunneling (BBT) of hot carriers from the gate-to-drain which can result in gate-induced drain leakage current, drain current fluctuation, voltage drop in the gate area, threshold voltage shift in the MOS transistors, and the like.
Impurities (such as contaminants, metals, and the like) may, for example, be introduced at the oxide layer/semiconductor interface of MOS transistors during oxidation processing, plasma deposition, etching or other processing steps. There is therefore a need to determine the quality of these interfaces prior to or during the manufacture of semiconductor devices on the wafer. Interface trap charge pumping is a well-known transient recombination effect that is activated by cycling or pumping the Si—SiO2 interface of the MOSFET between accumulation and inversion states. Charge-pumping measurements can then be used to extract or determine interface trap density, and the effect of gate leakage can be compensated for by measuring charge-pumping current at a low frequency, for example, and then subtracting it from measurement results at higher frequencies.
Basic charge-pumping techniques involve measuring the substrate output current while applying input voltage pulses of fixed amplitude, rise time, fall time, and frequency to the gate of the transistor, with the source, drain, and body tied to ground, for example. The electrical pulse can be applied with a fixed amplitude, a voltage base sweep, a fixed base, a variable amplitude sweep, and the like. The charge pumping method can evaluate the surface states at the Si—SiO2 interface of MOSFET devices, for example.
The traditional charge pumping technique for characterizing interface traps fails when tunneling current is comparable to or greater than the charge pumping current, as it is difficult to separate the two currents. A priori estimation of the average gate tunneling current (which is a function of the gate voltage waveform) into the bulk or source/drain of the MOSFET during charge pumping leads to inaccuracies due to the exponential dependence of gate tunneling current on the gate voltage.
FIG. 1 shows a typical conventional setup 100, illustrating the use of a pulse generator 102 to apply a square or trapezoidal pulse wave to a gate 104 that overlies a thin gate oxide 108 of a metal oxide semiconductor field effect transistor (MOSFET) 106. The pulse wave may be square or trapezoidal, or a linear combination of both. Moreover, the pulse wave may be triangular, sinusoidal, rectangular, comb-shaped, or have some other configuration. As illustrated, a source 110 and drain 112 are both shorted together and grounded while measuring the current output (Isub) at a current measuring device 114. As a positive or negative bias is applied to the gate 104, the surface of the MOSFET accumulates or inverts, respectively, and if there are interface traps located at the gate oxide/bulk substrate interface (viz., Si—SiO2 interface), the traps will tend to go back to either the conduction band or the valence band, depending on the type of traps present. By pulsating the interface traps rapidly, the technique takes advantage of the fact that traps have only a finite response time, therefore only some of the traps will go back to the conduction or valence band. However, some of the traps will remain “trapped” and recombine with the inversion charge or the accumulation charge coming from the bulk.
There is a substantial current measurement difference between devices, when evaluating an enhanced complementary metal oxide semiconductor (CMOS) as opposed to a MOSFET where the gate dielectric is very thin. Utilizing a thin gate dielectric, if there is an increase in the voltage beyond inversion, or if the device is taken to deep accumulation, a significant amount of gate current will result. However, this gate current is small, when compared to a normal MOSFET operating current, which is the source/drain current. The current measured is a very small current, many orders of magnitude lower than the normal device current. In an advanced CMOS device, the magnitude of the tunneling current approaches and often exceeds the magnitude of the charge pumping current for the density of interface traps of interest. These values can range from tens to hundreds of picoamps per square micron.
Thus, there is a need to provide a method for measuring interface traps in thin gate oxide MOSFETs that overcomes the previously mentioned problems.